1. 設定專案前確認電腦的Windows安裝與設定。
a. 安裝Visual Studio Code，並設定好支援Verilog語法插件。
b. 安裝編譯與模擬波形的QuestaSim。
c. 下載Mingw-w64與設定環境變數。
2. 設定專案資料夾，如下圖所示。
3. 專案資料夾"Sample"下，sim下增加wave.do的Tcl script，src下為自己設計的RTL code，tb下為testbench，Makefile放在專案資料夾下，如下圖所示。
4. 開啟Visual Studio Code編輯程序。
########Test.v########
module Test(a, b, c, d, En, Sel, f);
input a, b, c, d, En, Sel;
output f;
wire f;
wire g, h, i, j;
assign g = a | b;
assign i = g & En;
assign h = c | d;
assign j = h & En;
assign f = (Sel==1'b0) ? i : j;
endmodule
########testbench.v########
`timescale 1ns / 1ns
module testbench;
reg a, b, c, d, En, Sel;
wire f;
Test UUT(
.a(a),
.b(b),
.c(c),
.d(d),
.En(En),
.Sel(Sel),
.f(f) );
initial
begin
a = 1'b0; // Time = 0
b = 1'b1;
c = 1'b0;
d = 1'b1;
En = 1'b0;
Sel = 1'b0;
#20; // Time = 20
a = 1'b1;
#10; // Time = 30
b = 1'b0;
c = 1'b1;
#10; // Time = 40
a = 1'b0;
#10; // Time = 50
En = 1'b1;
#10; // Time = 60
c = 1'b0;
#10; // Time = 70
a = 1'b1;
d = 1'b0;
#20; // Time = 90
c = 1'b1;
#20; // Time = 110
a = 1'b0;
#10; // Time = 120
a = 1'b1;
#10; // Time = 130
c = 1'b0;
Sel= 1'b1;
#10; // Time = 140
a = 1'b0;
#30; // Time = 170
a = 1'b1;
#10; // Time = 180
c = 1'b1;
#20; // Time = 200
a = 1'b0;
end
endmodule
########wave.do########
#QuestaSim's Tcl script
view wave
log -r /*
#add wave -r /*
#add wave -group "IO" sim:/testbench/*
add wave -group "INPUTS" sim:/testbench/UUT/a
add wave -group "INPUTS" sim:/testbench/UUT/b
add wave -group "INPUTS" sim:/testbench/UUT/c
add wave -group "INPUTS" sim:/testbench/UUT/d
add wave -group "INPUTS" sim:/testbench/UUT/En
add wave -group "INPUTS" sim:/testbench/UUT/Sel
add wave -group "OUTPUTS" sim:/testbench/UUT/f
run -all
########Makefile########
# ========= Project Configuration =========
TOP = testbench
SRC_DIR = src
TB_DIR = tb
SIM_DIR = sim
LOG_DIR = log
LIB = work
# Automatically collect Verilog files
SRC = $(wildcard $(SRC_DIR)/*.v)
TB = $(wildcard $(TB_DIR)/*.v)
# ========= QuestaSim Path =========
QUESTA_HOME = C:/questasim64_10.6c/win64
VLIB = $(QUESTA_HOME)/vlib
VMAP = $(QUESTA_HOME)/vmap
VLOG = $(QUESTA_HOME)/vlog
VSIM = $(QUESTA_HOME)/vsim
# Log files
VLOG_LOG = $(LOG_DIR)/compile.log
VSIM_LOG = $(LOG_DIR)/sim.log
# ========= Default Target =========
.PHONY: build run wave debug rebuild clean
.DEFAULT_GOAL := build
# ========= Create log directory =========
$(LOG_DIR):
@if not exist $(LOG_DIR) mkdir $(LOG_DIR)
# ========= Compile =========
build: $(LOG_DIR)
@echo [INFO] Compiling design...
@if exist $(LIB) rmdir /s /q $(LIB)
$(VLIB) $(LIB)
$(VMAP) $(LIB) $(LIB)
$(VLOG) $(SRC) $(TB) > $(VLOG_LOG)
# ========= Run (CLI) =========
run: build
@echo [INFO] Running simulation (CLI)...
$(VSIM) -c $(TOP) -do "run -all; quit -f" > $(VSIM_LOG)
# ========= GUI + Wave =========
wave: build
$(VSIM) -gui -voptargs="+acc +fsmdebug" -debugDB $(TOP) -do "$(SIM_DIR)/wave.do"
# ========= Debug =========
debug: rebuild wave
# ========= Rebuild =========
rebuild: clean build
# ========= Clean =========
clean:
@echo [INFO] Cleaning project...
@if exist $(LIB) rmdir /s /q $(LIB)
@if exist transcript del /q transcript
@if exist vsim.wlf del /q vsim.wlf
@if exist *.dbg del /q *.dbg
@if exist vsim_stacktrace.vstf del /q vsim_stacktrace.vstf
@if exist modelsim.ini del /q modelsim.ini
@if exist $(LOG_DIR) rmdir /s /q $(LOG_DIR)
5. 輸入完成，在Visual Studio Code開啟Terminal如步驟4圖示，輸入"make debug"，顯示波形如下圖所示。
