/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8_003x_H
#define __STM8_003x_H
#include "stm8s_type.h"
/******************************************************************************/
/* Library configuration section */
/******************************************************************************/
/******************************************************************************/
/* Peripherals Base Address */
/******************************************************************************/
#define GPIOA_BaseAddress 0x5000
#define GPIOB_BaseAddress 0x5005
#define GPIOC_BaseAddress 0x500A
#define GPIOD_BaseAddress 0x500F
#define GPIOE_BaseAddress 0x5014
#define GPIOF_BaseAddress 0x5019
#define FLASH_BaseAddress 0x505A
#define ITC_BaseAddress 0x50A0
#define RST_BaseAddress 0x50B3
#define CLK_BaseAddress 0x50C3
#define WWDG_BaseAddress 0x50D1
#define IWDG_BaseAddress 0x50E0
#define AWU_BaseAddress 0x50F0
#define BEEP_BaseAddress 0x50F3
#define SPI_BaseAddress 0x5200
#define I2C_BaseAddress 0x5210
#define UART1_BaseAddress 0x5230
#define TIM1_BaseAddress 0x5250
#define TIM2_BaseAddress 0x5300
#define TIM4_BaseAddress 0x5340
#define ADC1_BaseAddress 0x53E0
/******************************************************************************/
/* Peripherals declarations */
/******************************************************************************/
#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
#define RST ((RST_TypeDef *) RST_BaseAddress)
#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
#define AWU ((AWU_TypeDef *) AWU_BaseAddress)
#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
#define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
#define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
#define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
#define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
#define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
#define disableInterrupts() {_asm("sim\n");} /* disable interrupts */
/* @brief General Purpose I/Os (GPIO) */
typedef struct GPIO_struct
{
vu8 ODR; /*!< Output Data Register */
vu8 IDR; /*!< Input Data Register */
vu8 DDR; /*!< Data Direction Register */
vu8 CR1; /*!< Configuration Register 1 */
vu8 CR2; /*!< Configuration Register 2 */
}GPIO_TypeDef;
/* @brief FLASH program and Data memory (FLASH) */
typedef struct FLASH_struct
{
vu8 CR1; /*!< Flash control register 1 */
vu8 CR2; /*!< Flash control register 2 */
vu8 NCR2; /*!< Flash complementary control register 2 */
vu8 FPR; /*!< Flash protection register */
vu8 NFPR; /*!< Flash complementary protection register */
vu8 IAPSR; /*!< Flash in-application programming status register */
u8 RESERVED1; /*!< Reserved byte */
u8 RESERVED2; /*!< Reserved byte */
vu8 PUKR; /*!< Flash program memory unprotection register */
u8 RESERVED3; /*!< Reserved byte */
vu8 DUKR; /*!< Data EEPROM unprotection register */
}FLASH_TypeDef;
/* @brief Interrupt Controller (ITC) */
typedef struct ITC_struct
{
vu8 CR1; /*!< External interrupt control register 1 */
vu8 CR2; /*!< External interrupt control register 2 */
}ITC_TypeDef;
/* @brief Reset Controller (RST) */
typedef struct RST_struct
{
vu8 SR; /*!< Reset status register */
}RST_TypeDef;
/* @brief Clock Controller (CLK) */
typedef struct CLK_struct
{
vu8 ICKR; /*!< Internal Clocks Control Register */
vu8 ECKR; /*!< External Clocks Control Register */
u8 RESERVED; /*!< Reserved byte */
vu8 CMSR; /*!< Clock Master Status Register */
vu8 SWR; /*!< Clock Master Switch Register */
vu8 SWCR; /*!< Switch Control Register */
vu8 CKDIVR; /*!< Clock Divider Register */
vu8 PCKENR1; /*!< Peripheral Clock Gating Register 1 */
vu8 CSSR; /*!< Clock Security Sytem Register */
vu8 CCOR; /*!< Configurable Clock Output Register */
vu8 PCKENR2; /*!< Peripheral Clock Gating Register 2 */
vu8 CANCCR; /*!< CAN external clock control Register (exist only in STM8S208 otherwise it is reserved) */
vu8 HSITRIMR; /*!< HSI Calibration Trimmer Register */
vu8 SWIMCCR; /*!< SWIM clock control register */
}CLK_TypeDef;
/* @brief Window Watchdog (WWDG) */
typedef struct WWDG_struct
{
vu8 CR; /*!< Control Register */
vu8 WR; /*!< Window Register */
}WWDG_TypeDef;
/* @brief Independent Watchdog (IWDG) */
typedef struct IWDG_struct
{
vu8 KR; /*!< Key Register */
vu8 PR; /*!< Prescaler Register */
vu8 RLR; /*!< Reload Register */
}IWDG_TypeDef;
/* @brief Auto Wake Up (AWU) peripheral registers. */
typedef struct AWU_struct
{
vu8 CSR; /*!< AWU Control status register */
vu8 APR; /*!< AWU Asynchronous prescaler buffer */
vu8 TBR; /*!< AWU Time base selection register */
}AWU_TypeDef;
/* @brief Beeper (BEEP) peripheral registers. */
typedef struct BEEP_struct
{
vu8 CSR; /*!< BEEP Control status register */
}BEEP_TypeDef;
/* @brief Serial Peripheral Interface (SPI) */
typedef struct SPI_struct
{
vu8 CR1; /*!< SPI control register 1 */
vu8 CR2; /*!< SPI control register 2 */
vu8 ICR; /*!< SPI interrupt control register */
vu8 SR; /*!< SPI status register */
vu8 DR; /*!< SPI data I/O register */
vu8 CRCPR; /*!< SPI CRC polynomial register */
vu8 RXCRCR; /*!< SPI Rx CRC register */
vu8 TXCRCR; /*!< SPI Tx CRC register */
}SPI_TypeDef;
/* @brief Inter-Integrated Circuit (I2C) */
typedef struct I2C_struct
{
vu8 CR1; /*!< I2C control register 1 */
vu8 CR2; /*!< I2C control register 2 */
vu8 FREQR; /*!< I2C frequency register */
vu8 OARL; /*!< I2C own address register LSB */
vu8 OARH; /*!< I2C own address register MSB */
u8 RESERVED1; /*!< Reserved byte */
vu8 DR; /*!< I2C data register */
vu8 SR1; /*!< I2C status register 1 */
vu8 SR2; /*!< I2C status register 2 */
vu8 SR3; /*!< I2C status register 3 */
vu8 ITR; /*!< I2C interrupt register */
vu8 CCRL; /*!< I2C clock control register low */
vu8 CCRH; /*!< I2C clock control register high */
vu8 TRISER; /*!< I2C maximum rise time register */
vu8 PECR; /*!< I2C packet error checking register */
}I2C_TypeDef;
/* @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1) */
typedef struct UART1_struct
{
vu8 SR; /*!< UART1 status register */
vu8 DR; /*!< UART1 data register */
vu8 BRR1; /*!< UART1 baud rate register */
vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
vu8 CR1; /*!< UART1 control register 1 */
vu8 CR2; /*!< UART1 control register 2 */
vu8 CR3; /*!< UART1 control register 3 */
vu8 CR4; /*!< UART1 control register 4 */
vu8 CR5; /*!< UART1 control register 5 */
vu8 CR6; /*!< UART1 control register 6 */
vu8 GTR; /*!< UART1 guard time register */
vu8 PSCR; /*!< UART1 prescaler register */
}UART1_TypeDef;
/* @brief 16-bit timer with complementary PWM outputs (TIM1) */
typedef struct TIM1_struct
{
vu8 CR1; /*!< control register 1 */
vu8 CR2; /*!< control register 2 */
vu8 SMCR; /*!< Synchro mode control register */
vu8 ETR; /*!< external trigger register */
vu8 IER; /*!< interrupt enable register*/
vu8 SR1; /*!< status register 1 */
vu8 SR2; /*!< status register 2 */
vu8 EGR; /*!< event generation register */
vu8 CCMR1; /*!< CC mode register 1 */
vu8 CCMR2; /*!< CC mode register 2 */
vu8 CCMR3; /*!< CC mode register 3 */
vu8 CCMR4; /*!< CC mode register 4 */
vu8 CCER1; /*!< CC enable register 1 */
vu8 CCER2; /*!< CC enable register 2 */
vu8 CNTRH; /*!< counter high */
vu8 CNTRL; /*!< counter low */
vu8 PSCRH; /*!< prescaler high */
vu8 PSCRL; /*!< prescaler low */
vu8 ARRH; /*!< auto-reload register high */
vu8 ARRL; /*!< auto-reload register low */
vu8 RCR; /*!< Repetition Counter register */
vu8 CCR1H; /*!< capture/compare register 1 high */
vu8 CCR1L; /*!< capture/compare register 1 low */
vu8 CCR2H; /*!< capture/compare register 2 high */
vu8 CCR2L; /*!< capture/compare register 2 low */
vu8 CCR3H; /*!< capture/compare register 3 high */
vu8 CCR3L; /*!< capture/compare register 3 low */
vu8 CCR4H; /*!< capture/compare register 3 high */
vu8 CCR4L; /*!< capture/compare register 3 low */
vu8 BKR; /*!< Break Register */
vu8 DTR; /*!< dead-time register */
vu8 OISR; /*!< Output idle register */
}TIM1_TypeDef;
/* @brief 16-bit timer (TIM2) */
typedef struct TIM2_struct
{
vu8 CR1; /*!< control register 1 */
u8 RESERVED1; /*!< Reserved register */
u8 RESERVED2; /*!< Reserved register */
vu8 IER; /*!< interrupt enable register */
vu8 SR1; /*!< status register 1 */
vu8 SR2; /*!< status register 2 */
vu8 EGR; /*!< event generation register */
vu8 CCMR1; /*!< CC mode register 1 */
vu8 CCMR2; /*!< CC mode register 2 */
vu8 CCMR3; /*!< CC mode register 3 */
vu8 CCER1; /*!< CC enable register 1 */
vu8 CCER2; /*!< CC enable register 2 */
vu8 CNTRH; /*!< counter high */
vu8 CNTRL; /*!< counter low */
vu8 PSCR; /*!< prescaler register */
vu8 ARRH; /*!< auto-reload register high */
vu8 ARRL; /*!< auto-reload register low */
vu8 CCR1H; /*!< capture/compare register 1 high */
vu8 CCR1L; /*!< capture/compare register 1 low */
vu8 CCR2H; /*!< capture/compare register 2 high */
vu8 CCR2L; /*!< capture/compare register 2 low */
vu8 CCR3H; /*!< capture/compare register 3 high */
vu8 CCR3L; /*!< capture/compare register 3 low */
}TIM2_TypeDef;
/* @brief 8-bit system timer (TIM4) */
typedef struct TIM4_struct
{
vu8 CR1; /*!< control register 1 */
u8 RESERVED1; /*!< Reserved1 byte */
u8 RESERVED2; /*!< Reserved2 byte */
vu8 IER; /*!< interrupt enable register */
vu8 SR; /*!< status register */
vu8 EGR; /*!< event generation register */
vu8 CNTR; /*!< counter register */
vu8 PSCR; /*!< prescaler register */
vu8 ARR; /*!< auto-reload register */
}TIM4_TypeDef;
/* @brief Analog to Digital Converter (ADC1) */
typedef struct ADC1_struct
{
vu8 DB0RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB0RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB1RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB1RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB2RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB2RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB3RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB3RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB4RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB4RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB5RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB5RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB6RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB6RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB7RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB7RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB8RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB8RL; /*!< ADC1 Data Buffer Register (LSB) */
vu8 DB9RH; /*!< ADC1 Data Buffer Register (MSB) */
vu8 DB9RL; /*!< ADC1 Data Buffer Register (LSB) */
u8 RESERVED[12]; /*!< Reserved byte */
vu8 CSR; /*!< ADC1 control status register */
vu8 CR1; /*!< ADC1 configuration register 1 */
vu8 CR2; /*!< ADC1 configuration register 2 */
vu8 CR3; /*!< ADC1 configuration register 3 */
vu8 DRH; /*!< ADC1 Data high */
vu8 DRL; /*!< ADC1 Data low */
vu8 TDRH; /*!< ADC1 Schmitt trigger disable register high */
vu8 TDRL; /*!< ADC1 Schmitt trigger disable register low */
vu8 HTRH; /*!< ADC1 high threshold register High*/
vu8 HTRL; /*!< ADC1 high threshold register Low*/
vu8 LTRH; /*!< ADC1 low threshold register high */
vu8 LTRL; /*!< ADC1 low threshold register low */
vu8 AWSRH; /*!< ADC1 watchdog status register high */
vu8 AWSRL; /*!< ADC1 watchdog status register low */
vu8 AWCRH; /*!< ADC1 watchdog control register high */
vu8 AWCRL; /*!< ADC1 watchdog control register low */
}ADC1_TypeDef;
#endif /* __STM8S_003x_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
請問大大,ST8 跟 51架構有什麼不同呢,感覺好難喔。
回覆刪除除了都是8bit的核心外,架構差異還蠻大的,暫存器的宣告方式都不一樣,STM8S的MCU 架構跟目前32bit 的MCU在程式風格上撰寫的方式比較接近,8051 與 STM8S 光是GPIO port的控制方式就有很大的區別.
刪除例如:
8051控制GPIO的方式:
假設寫一筆data
P1 = 0xFF;
讀一筆data
u8 x;
x = P1;
STM8S控制GPIO的方式:
先要將GPIO做初始化,先設定GPIO的暫存器,哪一個bit是要input還是output.
GPIOD->DDR |= 0x20;
GPIOD->CR1 |= 0x20;
GPIOD->CR2 |= 0x20;
之後要input的方式如下,
u8 i;
i = GPIOD->IDR;
那output的方式就如下所示,
GPIOD->ODR &= ~(0x20); //pull low
GPIOD->ODR |= 0x20; //pull high
另外像是Interrupt,Time的暫存器設定也是有差異的,另外我之前使用的是標準8051所以I2C,SPI,都是沒有的需要韌體工程師自己開發,而STM8S都是IC內部的硬體就已經設計好.
我覺得如果您是8bit MCU初學者,建議先學8051,因為8051 + Keil C(IDE開發環境)在台灣使用的人比較多,書籍比較齊全,STM8S在台灣比較冷門,教學的書籍可能要看中國大陸出板的簡體書籍.
板主大大,看了你的Blog後,感覺你對51非常的嫻熟,最近我們公司有缺人,不知道你有沒有意願,期待你能加入我們 ^_^
回覆刪除感謝您的賞識,撰寫Blog是自己在開發經驗上的紀錄,順便可以跟有相同工作經驗網友相互討論.
刪除