STM8S-Discovery_STM8S003F3-11_SPI

        STM8S MCU的SPI是使用Hardware設計,與標準8051的SPI是在Firmware開發,使用I/O PIN模擬SPI Write與Read的波形,是有些差異的,使用Hardware設計的SPI在傳輸速度上可以提升非常多,在使用上也變得比Firmware開發簡單很多.
        程式中使用的"#define Dummy 0x00"設定，是因為SPI的Clock是由MCU產生，STM8S是標準4線式的SPI介面，SI與SO pin可以同時做輸入與輸出的動作，當要使用SPI介面讀取其他IC的值時只要給MCU的"SPI->DR"暫存器一個Dummy的值就會產生SPI Read時所需要的Clock。

1. 整個project的程式檔案目錄如下圖所示.

2.  main.c

/***********************************************/
#include "stm8s_003x.h"
#include "stm8s_type.h"
#include "gpio.h"
#include "spi.h"

#define Dummy 0x00 //for SPI Clock

u8 ReadData;

int main(void)
{
enableInterrupts(); //InterruptInit

GPIOE_Init();
SPI_Init();

GPIOE->ODR &= ~(0x20); //NSS(CS) pull low.

SPI_IO(0xAA); //SPI write data
ReadData = SPI_IO(Dummy); //SPI read data

GPIOE->ODR |= 0x20; //NSS(CS) pull high.

return 0;
}

/***********************************************/

3.  gpio.c

/***********************************************/
#include "stm8s_003x.h"
#include "stm8s_type.h"
#include "gpio.h"

void GPIOE_Init(void)
{
GPIOE->DDR |= 0x20;
  GPIOE->CR1 |= 0x20;
GPIOE->CR2 |= 0x00;
}
/***********************************************/

4.  spi.c

/***********************************************/
#include "stm8s_003x.h"
#include "stm8s_type.h"
#include "spi.h"

void SPI_Init(void)
{
SPI->CR1 |= 0x07; //Master configuration
SPI->CR2 |= 0x03; //Master mode, Software slave management enabled.

SPI->CR1 |= 0x40; //SPI enable
GPIOE->ODR |= 0x20; //NSS(CS) pull high.
}

u8 SPI_IO(u8 OutputData)
{
u8 InputData;

while(! (SPI->SR & 0x02)); //Transmit buffer empty.
SPI->DR = OutputData; //Output Data.
while(! (SPI->SR & 0x01)); //Receive buffer not empty.
InputData = SPI->DR; //Input Data.

return InputData; //Input Data.
}
/***********************************************/

5.  stm8_interrupt_vector.c

/***********************************************/
/* BASIC INTERRUPT VECTOR TABLE FOR STM8 devices
 * Copyright (c) 2007 STMicroelectronics
 */

typedef void @far (*interrupt_handler_t)(void);

struct interrupt_vector {
unsigned char interrupt_instruction;
interrupt_handler_t interrupt_handler;
};

@far @interrupt void NonHandledInterrupt (void)
{
/* in order to detect unexpected events during development, 
  it is recommended to set a breakpoint on the following instruction
*/
return;
}

extern void _stext();     /* startup routine */

struct interrupt_vector const _vectab[] = {
{0x82, (interrupt_handler_t)_stext}, /* reset */
{0x82, NonHandledInterrupt}, /* trap  */
{0x82, NonHandledInterrupt}, /* irq0  */
{0x82, NonHandledInterrupt}, /* irq1  */
{0x82, NonHandledInterrupt}, /* irq2  */
{0x82, NonHandledInterrupt}, /* irq3  */
{0x82, NonHandledInterrupt}, /* irq4  */
{0x82, NonHandledInterrupt}, /* irq5  */
{0x82, NonHandledInterrupt}, /* irq6  */
{0x82, NonHandledInterrupt}, /* irq7  */
{0x82, NonHandledInterrupt}, /* irq8  */
{0x82, NonHandledInterrupt}, /* irq9  */
{0x82, NonHandledInterrupt}, /* irq10 */
{0x82, NonHandledInterrupt}, /* irq11 */
{0x82, NonHandledInterrupt}, /* irq12 */
{0x82, NonHandledInterrupt}, /* irq13 */
{0x82, NonHandledInterrupt}, /* irq14 */
{0x82, NonHandledInterrupt}, /* irq15 */
{0x82, NonHandledInterrupt}, /* irq16 */
{0x82, NonHandledInterrupt}, /* irq17 */
{0x82, NonHandledInterrupt}, /* irq18 */
{0x82, NonHandledInterrupt}, /* irq19 */
{0x82, NonHandledInterrupt}, /* irq20 */
{0x82, NonHandledInterrupt}, /* irq21 */
{0x82, NonHandledInterrupt}, /* irq22 */
{0x82, NonHandledInterrupt}, /* irq23 */
{0x82, NonHandledInterrupt}, /* irq24 */
{0x82, NonHandledInterrupt}, /* irq25 */
{0x82, NonHandledInterrupt}, /* irq26 */
{0x82, NonHandledInterrupt}, /* irq27 */
{0x82, NonHandledInterrupt}, /* irq28 */
{0x82, NonHandledInterrupt}, /* irq29 */

};

/***********************************************/

6.  gpio.h

/***********************************************/
#include "stm8s_type.h"


void GPIOE_Init(void);

/***********************************************/

7.  spi.h

/***********************************************/
#include "stm8s_type.h"

void SPI_Init(void);

u8 SPI_IO(u8 OutputData);
/***********************************************/

8.  stm8s_003x.h

/***********************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8_003x_H
#define __STM8_003x_H

#include "stm8s_type.h"
/******************************************************************************/
/*                   Library configuration section                            */
/******************************************************************************/

/******************************************************************************/
/*                          Peripherals Base Address                          */
/******************************************************************************/
#define GPIOA_BaseAddress       0x5000
#define GPIOB_BaseAddress       0x5005
#define GPIOC_BaseAddress       0x500A
#define GPIOD_BaseAddress       0x500F
#define GPIOE_BaseAddress       0x5014
#define GPIOF_BaseAddress       0x5019
#define FLASH_BaseAddress       0x505A
#define ITC_BaseAddress         0x50A0
#define RST_BaseAddress         0x50B3
#define CLK_BaseAddress         0x50C3
#define WWDG_BaseAddress       0x50D1
#define IWDG_BaseAddress       0x50E0
#define AWU_BaseAddress         0x50F0
#define BEEP_BaseAddress        0x50F3
#define SPI_BaseAddress         0x5200
#define I2C_BaseAddress         0x5210
#define UART1_BaseAddress       0x5230
#define TIM1_BaseAddress        0x5250
#define TIM2_BaseAddress        0x5300
#define TIM4_BaseAddress        0x5340
#define ADC1_BaseAddress        0x53E0


/******************************************************************************/
/*                          Peripherals declarations                          */
/******************************************************************************/

#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
#define RST ((RST_TypeDef *) RST_BaseAddress)
#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
#define AWU ((AWU_TypeDef *) AWU_BaseAddress)
#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
#define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
#define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
#define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
#define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)

/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/

#define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
#define disableInterrupts() {_asm("sim\n");} /* disable interrupts */

/* @brief  General Purpose I/Os (GPIO) */

typedef struct GPIO_struct
{
  vu8 ODR; /*!< Output Data Register */
  vu8 IDR; /*!< Input Data Register */
  vu8 DDR; /*!< Data Direction Register */
  vu8 CR1; /*!< Configuration Register 1 */
  vu8 CR2; /*!< Configuration Register 2 */
}GPIO_TypeDef;

/* @brief  Serial Peripheral Interface (SPI) */

typedef struct SPI_struct
{
  vu8 CR1;    /*!< SPI control register 1 */
  vu8 CR2;    /*!< SPI control register 2 */
  vu8 ICR;    /*!< SPI interrupt control register */
  vu8 SR;     /*!< SPI status register */
  vu8 DR;     /*!< SPI data I/O register */
  vu8 CRCPR;  /*!< SPI CRC polynomial register */
  vu8 RXCRCR; /*!< SPI Rx CRC register */
  vu8 TXCRCR; /*!< SPI Tx CRC register */
}SPI_TypeDef;

#endif /* __STM8S_003x_H */


/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

/***********************************************/

9.  stm8s_type.h

/***********************************************/
/**
  ******************************************************************************
  * @file stm8s_type.h
  * @brief This file contains all common data types.
  * @author STMicroelectronics - MCD Application Team
  * @version V1.1.1
  * @date 06/05/2009
  ******************************************************************************
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
  * @image html logo.bmp
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8S_TYPE_H
#define __STM8S_TYPE_H

/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
typedef signed long  s32;
typedef signed short s16;
typedef signed char  s8;

typedef signed long  const sc32;  /* Read Only */
typedef signed short const sc16;  /* Read Only */
typedef signed char  const sc8;   /* Read Only */

typedef volatile signed long  vs32;
typedef volatile signed short vs16;
typedef volatile signed char  vs8;

typedef volatile signed long  const vsc32;  /* Read Only */
typedef volatile signed short const vsc16;  /* Read Only */
typedef volatile signed char  const vsc8;   /* Read Only */

typedef unsigned long  u32;
typedef unsigned short u16;
typedef unsigned char  u8;

typedef unsigned long  const uc32;  /* Read Only */
typedef unsigned short const uc16;  /* Read Only */
typedef unsigned char  const uc8;   /* Read Only */

typedef volatile unsigned long  vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char  vu8;

typedef volatile unsigned long  const vuc32;  /* Read Only */
typedef volatile unsigned short const vuc16;  /* Read Only */
typedef volatile unsigned char  const vuc8;   /* Read Only */

typedef enum
{
  FALSE = 0,
  TRUE = !FALSE
}bool;

typedef enum 
{
  RESET = 0,
  SET = !RESET
}FlagStatus, ITStatus, BitStatus;

typedef enum
{
  DISABLE = 0,
  ENABLE = !DISABLE
}FunctionalState;

#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) )

typedef enum
{
  ERROR = 0,
  SUCCESS = !ERROR
}ErrorStatus;

#define U8_MAX     ((u8)255)
#define S8_MAX     ((s8)127)
#define S8_MIN     ((s8)-128)
#define U16_MAX    ((u16)65535u)
#define S16_MAX    ((s16)32767)
#define S16_MIN    ((s16)-32768)
#define U32_MAX    ((u32)4294967295uL)
#define S32_MAX    ((s32)2147483647)
#define S32_MIN    ((s32)-2147483648)

/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

#endif /* __STM8S_TYPE_H */


/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

/***********************************************/

STM8S-Discovery_STM8S003F3-10_錯誤訊息(ERROR: before starting debug session, please, select a target.)

    在按"Start Debugging"按鈕後，跳出"ERROR: before starting debug session, please, select a target."錯誤訊息時，表示Target的裝置沒有設定。

這時請按下"Target Settings"按鈕，選擇"Swim ST-Link"，按"確定"就可以了

STM8S-Discovery_STM8S003F3-9_Register map設定

STM8S不同的IC型號Register map設定都會有些差異,下列所示是for STM8S003F3.


/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8_003x_H
#define __STM8_003x_H

#include "stm8s_type.h"
/******************************************************************************/
/*                   Library configuration section                            */
/******************************************************************************/

/******************************************************************************/
/*                          Peripherals Base Address                          */
/******************************************************************************/
#define GPIOA_BaseAddress       0x5000
#define GPIOB_BaseAddress       0x5005
#define GPIOC_BaseAddress       0x500A
#define GPIOD_BaseAddress       0x500F
#define GPIOE_BaseAddress       0x5014
#define GPIOF_BaseAddress       0x5019
#define FLASH_BaseAddress       0x505A
#define ITC_BaseAddress         0x50A0
#define RST_BaseAddress         0x50B3
#define CLK_BaseAddress         0x50C3
#define WWDG_BaseAddress       0x50D1
#define IWDG_BaseAddress       0x50E0
#define AWU_BaseAddress         0x50F0
#define BEEP_BaseAddress        0x50F3
#define SPI_BaseAddress         0x5200
#define I2C_BaseAddress         0x5210
#define UART1_BaseAddress       0x5230
#define TIM1_BaseAddress        0x5250
#define TIM2_BaseAddress        0x5300
#define TIM4_BaseAddress        0x5340
#define ADC1_BaseAddress        0x53E0


/******************************************************************************/
/*                          Peripherals declarations                          */
/******************************************************************************/

#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
#define GPIOF  ((GPIO_TypeDef *)  GPIOF_BaseAddress)
#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
#define RST ((RST_TypeDef *) RST_BaseAddress)
#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
#define AWU ((AWU_TypeDef *) AWU_BaseAddress)
#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
#define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
#define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
#define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
#define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)

/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/

#define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
#define disableInterrupts() {_asm("sim\n");} /* disable interrupts */

/* @brief  General Purpose I/Os (GPIO) */

typedef struct GPIO_struct
{
  vu8 ODR; /*!< Output Data Register */
  vu8 IDR; /*!< Input Data Register */
  vu8 DDR; /*!< Data Direction Register */
  vu8 CR1; /*!< Configuration Register 1 */
  vu8 CR2; /*!< Configuration Register 2 */
}GPIO_TypeDef;

/* @brief  FLASH program and Data memory (FLASH) */

typedef struct FLASH_struct
{
  vu8 CR1; /*!< Flash control register 1 */
  vu8 CR2; /*!< Flash control register 2 */
  vu8 NCR2; /*!< Flash complementary control register 2 */
  vu8 FPR; /*!< Flash protection register */
  vu8 NFPR; /*!< Flash complementary protection register */
  vu8 IAPSR; /*!< Flash in-application programming status register */
  u8 RESERVED1; /*!< Reserved byte */
  u8 RESERVED2; /*!< Reserved byte */
  vu8 PUKR; /*!< Flash program memory unprotection register */
  u8 RESERVED3; /*!< Reserved byte */
  vu8 DUKR; /*!< Data EEPROM unprotection register */
}FLASH_TypeDef;

/* @brief  Interrupt Controller (ITC) */

typedef struct ITC_struct
{
  vu8 CR1; /*!< External interrupt control register 1 */
  vu8 CR2; /*!< External interrupt control register 2 */
}ITC_TypeDef;

/* @brief  Reset Controller (RST) */

typedef struct RST_struct
{
  vu8 SR; /*!< Reset status register */
}RST_TypeDef;

/* @brief  Clock Controller (CLK) */

typedef struct CLK_struct
{
  vu8 ICKR;     /*!< Internal Clocks Control Register */
  vu8 ECKR;     /*!< External Clocks Control Register */
  u8 RESERVED; /*!< Reserved byte */
  vu8 CMSR;     /*!< Clock Master Status Register */
  vu8 SWR;      /*!< Clock Master Switch Register */
  vu8 SWCR;     /*!< Switch Control Register */
  vu8 CKDIVR;   /*!< Clock Divider Register */
  vu8 PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
  vu8 CSSR;     /*!< Clock Security Sytem Register */
  vu8 CCOR;     /*!< Configurable Clock Output Register */
  vu8 PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
  vu8 CANCCR;   /*!< CAN external clock control Register (exist only in STM8S208 otherwise it is reserved) */
  vu8 HSITRIMR; /*!< HSI Calibration Trimmer Register */
  vu8 SWIMCCR;  /*!< SWIM clock control register */
}CLK_TypeDef;

/* @brief  Window Watchdog (WWDG) */

typedef struct WWDG_struct
{
  vu8 CR; /*!< Control Register */
  vu8 WR; /*!< Window Register */
}WWDG_TypeDef;

/* @brief  Independent Watchdog (IWDG) */

typedef struct IWDG_struct
{
  vu8 KR;  /*!< Key Register */
  vu8 PR;  /*!< Prescaler Register */
  vu8 RLR; /*!< Reload Register */
}IWDG_TypeDef;

/* @brief  Auto Wake Up (AWU) peripheral registers. */

typedef struct AWU_struct
{
  vu8 CSR; /*!< AWU Control status register */
  vu8 APR; /*!< AWU Asynchronous prescaler buffer */
  vu8 TBR; /*!< AWU Time base selection register */
}AWU_TypeDef;

/* @brief  Beeper (BEEP) peripheral registers. */

typedef struct BEEP_struct
{
  vu8 CSR; /*!< BEEP Control status register */
}BEEP_TypeDef;

/* @brief  Serial Peripheral Interface (SPI) */

typedef struct SPI_struct
{
  vu8 CR1;    /*!< SPI control register 1 */
  vu8 CR2;    /*!< SPI control register 2 */
  vu8 ICR;    /*!< SPI interrupt control register */
  vu8 SR;     /*!< SPI status register */
  vu8 DR;     /*!< SPI data I/O register */
  vu8 CRCPR;  /*!< SPI CRC polynomial register */
  vu8 RXCRCR; /*!< SPI Rx CRC register */
  vu8 TXCRCR; /*!< SPI Tx CRC register */
}SPI_TypeDef;

/* @brief  Inter-Integrated Circuit (I2C) */

typedef struct I2C_struct
{
  vu8 CR1;       /*!< I2C control register 1 */
  vu8 CR2;       /*!< I2C control register 2 */
  vu8 FREQR;     /*!< I2C frequency register */
  vu8 OARL;      /*!< I2C own address register LSB */
  vu8 OARH;      /*!< I2C own address register MSB */
  u8 RESERVED1; /*!< Reserved byte */
  vu8 DR;        /*!< I2C data register */
  vu8 SR1;       /*!< I2C status register 1 */
  vu8 SR2;       /*!< I2C status register 2 */
  vu8 SR3;       /*!< I2C status register 3 */
  vu8 ITR;       /*!< I2C interrupt register */
  vu8 CCRL;      /*!< I2C clock control register low */
  vu8 CCRH;      /*!< I2C clock control register high */
  vu8 TRISER;    /*!< I2C maximum rise time register */
  vu8 PECR; /*!< I2C packet error checking register */
}I2C_TypeDef;

/* @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART1) */

typedef struct UART1_struct
{
  vu8 SR;   /*!< UART1 status register */
  vu8 DR;   /*!< UART1 data register */
  vu8 BRR1; /*!< UART1 baud rate register */
  vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
  vu8 CR1;  /*!< UART1 control register 1 */
  vu8 CR2;  /*!< UART1 control register 2 */
  vu8 CR3;  /*!< UART1 control register 3 */
  vu8 CR4;  /*!< UART1 control register 4 */
  vu8 CR5;  /*!< UART1 control register 5 */
vu8 CR6;  /*!< UART1 control register 6 */
  vu8 GTR;  /*!< UART1 guard time register */
  vu8 PSCR; /*!< UART1 prescaler register */
}UART1_TypeDef;

/* @brief  16-bit timer with complementary PWM outputs (TIM1) */

typedef struct TIM1_struct
{
  vu8 CR1;   /*!< control register 1 */
  vu8 CR2;   /*!< control register 2 */
  vu8 SMCR;  /*!< Synchro mode control register */
  vu8 ETR;   /*!< external trigger register */
  vu8 IER;   /*!< interrupt enable register*/
  vu8 SR1;   /*!< status register 1 */
  vu8 SR2;   /*!< status register 2 */
  vu8 EGR;   /*!< event generation register */
  vu8 CCMR1; /*!< CC mode register 1 */
  vu8 CCMR2; /*!< CC mode register 2 */
  vu8 CCMR3; /*!< CC mode register 3 */
  vu8 CCMR4; /*!< CC mode register 4 */
  vu8 CCER1; /*!< CC enable register 1 */
  vu8 CCER2; /*!< CC enable register 2 */
  vu8 CNTRH; /*!< counter high */
  vu8 CNTRL; /*!< counter low */
  vu8 PSCRH; /*!< prescaler high */
  vu8 PSCRL; /*!< prescaler low */
  vu8 ARRH;  /*!< auto-reload register high */
  vu8 ARRL;  /*!< auto-reload register low */
  vu8 RCR;   /*!< Repetition Counter register */
  vu8 CCR1H; /*!< capture/compare register 1 high */
  vu8 CCR1L; /*!< capture/compare register 1 low */
  vu8 CCR2H; /*!< capture/compare register 2 high */
  vu8 CCR2L; /*!< capture/compare register 2 low */
  vu8 CCR3H; /*!< capture/compare register 3 high */
  vu8 CCR3L; /*!< capture/compare register 3 low */
  vu8 CCR4H; /*!< capture/compare register 3 high */
  vu8 CCR4L; /*!< capture/compare register 3 low */
  vu8 BKR;   /*!< Break Register */
  vu8 DTR;   /*!< dead-time register */
  vu8 OISR;  /*!< Output idle register */
}TIM1_TypeDef;

/* @brief  16-bit timer (TIM2) */

typedef struct TIM2_struct
{
  vu8 CR1; /*!< control register 1 */
u8 RESERVED1; /*!< Reserved register */
u8 RESERVED2; /*!< Reserved register */
  vu8 IER; /*!< interrupt enable register */
  vu8 SR1; /*!< status register 1 */
  vu8 SR2; /*!< status register 2 */
  vu8 EGR; /*!< event generation register */
  vu8 CCMR1; /*!< CC mode register 1 */
  vu8 CCMR2; /*!< CC mode register 2 */
  vu8 CCMR3; /*!< CC mode register 3 */
  vu8 CCER1; /*!< CC enable register 1 */
  vu8 CCER2; /*!< CC enable register 2 */
  vu8 CNTRH; /*!< counter high */
  vu8 CNTRL; /*!< counter low */
  vu8 PSCR; /*!< prescaler register */
  vu8 ARRH; /*!< auto-reload register high */
  vu8 ARRL; /*!< auto-reload register low */
  vu8 CCR1H; /*!< capture/compare register 1 high */
  vu8 CCR1L; /*!< capture/compare register 1 low */
  vu8 CCR2H; /*!< capture/compare register 2 high */
  vu8 CCR2L; /*!< capture/compare register 2 low */
  vu8 CCR3H; /*!< capture/compare register 3 high */
  vu8 CCR3L; /*!< capture/compare register 3 low */
}TIM2_TypeDef;

/* @brief  8-bit system timer (TIM4) */

typedef struct TIM4_struct
{
  vu8 CR1;   /*!< control register 1 */
u8 RESERVED1; /*!< Reserved1 byte */
u8 RESERVED2; /*!< Reserved2 byte */
  vu8 IER;   /*!< interrupt enable register */
  vu8 SR;   /*!< status register */
  vu8 EGR;   /*!< event generation register */
  vu8 CNTR; /*!< counter register */
  vu8 PSCR; /*!< prescaler register */
  vu8 ARR;   /*!< auto-reload register */
}TIM4_TypeDef;

/* @brief  Analog to Digital Converter (ADC1) */

typedef struct ADC1_struct
{
  vu8 DB0RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB0RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB1RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB1RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB2RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB2RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB3RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB3RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB4RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB4RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB5RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB5RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB6RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB6RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB7RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB7RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB8RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB8RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB9RH;         /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB9RL;         /*!< ADC1 Data Buffer Register (LSB)  */
  u8 RESERVED[12];  /*!< Reserved byte */
  vu8 CSR;           /*!< ADC1 control status register */
  vu8 CR1;           /*!< ADC1 configuration register 1 */
  vu8 CR2;           /*!< ADC1 configuration register 2 */
  vu8 CR3;           /*!< ADC1 configuration register 3  */
  vu8 DRH;           /*!< ADC1 Data high */
  vu8 DRL;           /*!< ADC1 Data low */
  vu8 TDRH;          /*!< ADC1 Schmitt trigger disable register high */
  vu8 TDRL;          /*!< ADC1 Schmitt trigger disable register low */
  vu8 HTRH;          /*!< ADC1 high threshold register High*/
  vu8 HTRL;          /*!< ADC1 high threshold register Low*/
  vu8 LTRH;          /*!< ADC1 low threshold register high */
  vu8 LTRL;          /*!< ADC1 low threshold register low */
  vu8 AWSRH;         /*!< ADC1 watchdog status register high */
  vu8 AWSRL;         /*!< ADC1 watchdog status register low */
  vu8 AWCRH;         /*!< ADC1 watchdog control register high */
  vu8 AWCRL;         /*!< ADC1 watchdog control register low */
}ADC1_TypeDef;

#endif /* __STM8S_003x_H */

/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/