# A completely free and open architecture.
# A linear, 32-bit or 64-bit logical address space with implementation-specific physical
address space.
# Simple and uniform-length instruction formats featuring different instruction set
extensions:
# OpenRISC Basic Instruction Set (ORBIS32/64) with 32-bit wide instructions
aligned on 32-bit boundaries in memory and operating on 32- and 64-bit data
# OpenRISC Vector/DSP eXtension (ORVDX64) with 32-bit wide instructions
aligned on 32-bit boundaries in memory and operating on 8-, 16-, 32- and 64-bit
data
# OpenRISC Floating-Point eXtension (ORFPX32/64) with 32-bit wide instructions
aligned on 32-bit boundaries in memory and operating on 32- and 64-bit data
# Two simple memory addressing modes, whereby memory address is calculated by:
# addition of a register operand and a signed 16-bit immediate value
# addition of a register operand and a signed 16-bit immediate value followed by
update of the register operand with the calculated effective address
# Two register operands (or one register and a constant) for most instructions who then
place the result in a third register
# Shadowed or single 32-entry or narrow 16-entry general purpose register file
# Optional branch delay slot for keeping the pipeline as full as possible
# Support for separate instruction and data caches/MMUs (Harvard architecture) or for
unified instruction and data caches/MMUs (Stanford architecture)
# A flexible architecture definition that allows certain functions to be performed either
in hardware or with the assistance of implementation-specific software
# Number of different, separated exceptions simplifying exception model
# Fast context switch support in register set, caches, and MMUs
