OpenRISC 1000架構

The OpenRISC 1200 is an implementation of OpenRISC 1000 processor family.

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.

Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged. By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mapped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB. Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.

General Microarchitecture

• Central CPU/DSP block
• IEEE 754 compliant single precision FPU
• Direct mapped data cache
• Direct mapped instruction cache
• Data MMU based on hash-based DTLB
• Instruction MMU based on hash-based ITLB
• Power management unit and power management interface
• Tick timer
• Debug unit and development interface
• Interrupt controller and interrupt interface
• Instruction and Data WISHBONE B3 compliant interfaces