科技難.不難: 3月 2019

2019年3月28日星期四

ADP-XC5FF676平台開發SOC

不管是使用的Andes core CPU或者是使用ARM core CPU, 都一定會使用到AHB bus, 下圖是三星電子使用ARM core CPU 的chip (S3C2443為市面上最常見的MCU),且目前市面上可以買到的MCU或是ARM開發板都是沒有留AHB bus,而一般沒有留AHB bus(AMBA)的MCU是給系統業者開發一般消費性產品使用.

如果要是使用FPGA撰寫自己的IP(VHDL or Verilog),成為IC設計工程師,就必須使用AHB bus(AMBA)與CPU做溝通,這是一般IC設計業界在開發SOC時,都是使用這個方式,所以了解AHB bus(AMBA)是非常重要的.下圖是ADP-XC5FF676平台疊板設計SOC的架構圖.

下圖實際ADP-XC5FF676平台疊板的方式,上下疊板,下板FPGA內有Andes core CPU,上板是用Xilinx ISE燒錄自己所撰寫的IP cord(VHDL or Verilog).

ADP-XC5FF676平台開發SOC-XILINX FPGA Download Programming

A.XILINX FPGA download programming tools

1. Download cable.

2. XILINX ISE 9.2.03i.

http://www.xilinx.com/

B.Setup Hardware

1. 接上Download cable.
2. Power ON.

C.Download programming
1. 選擇Xilinx ISE 燒錄工具 iMPACT.

2. 選擇”create new project(.ipf)” 後,按”OK”.

3. 按”Finish”.

4. 選擇第一個元件後,按滑鼠右鍵,選擇”Assign New Configuration File”.

5. 選擇副檔名為.mcs燒錄檔後,按”Open”.

註解:
.mcs 燒錄至PROM,燒錄時間較久,但電源關閉後程式依然存在,適合已開發完成的程式.
.bit 燒錄時間較快,檔案燒錄後只會暫存,電源關閉後程式會消失,適合開發中的程式測試使用.
6. 按”Bypass”.

7.選擇第一個元件後,按滑鼠右鍵,選擇”Program”.

8. 依照圖示選擇後,按”OK”

9. 開始燒錄.

10.燒錄完成.

D.Programming OK將Power OFF後,重新Power NO.

After power-on reset(press GPIO[0])
0x00: boot start(reset_NMI)
0x01: init SDRAM configuration OK
0x02: SDRAM OK(compare ROM and SDRAM code)
0x04: copy vector table OK
0x05: init stack OK
0x06: init BSS OK
0x07: hardware init OK
0x7b: copy SDRAM OK(sleep mode)
0x7c: reset SDRAM conf.register OK
0x81: sleep wake up successful
0x82: sleep mode protection error
0x96: start to init SRAM
0x98: SDRAM error(compare ROM and SDRAM code)
0xE0: PMU presetting for AG101 chip

Interruption LED
0xb0: TLB_fill
0xb1: TLB_not_present
0xb2: TLB_misc
0xb3: TLB_VLPT_miss
0xb4: cache_parity_error
0xb5: debug
0xb6: general_exception
0xb7: flib_syscall
0xb8: external_interrupt
0xb9: HW0_interrupt
0x0A: HW1_interrupt
0x00: reset_NMI

0x99: boot preprocessor before displaying the diagnostic main menu

ADP-XC5FF676平台使用XILINX FPGA 與CPLD Platform Cable

1. XILINX 原廠USB　Platform Cable.
新加坡商安富利股份有限公司台灣分公司
XILINX事業群
http://www.avnet.com/

2. XILINX 原廠Ｐrint port Platform Cable.

3. XILINX副廠USB Platorm Cable.
依元素科技（E-Elements）
http://www.e-elements.com/tw/da.asp

建議購買３. XILINX 副廠USB　Platform Cable,筆記型電腦也可以使用,也較原廠便宜.

參考書籍-AndeShape TM ADP-XC5FF676 開發平台基礎實習手冊

作者：周志學/著
出版社：藍海文化
出版日期：2011年01月25日
語言：繁體中文 ISBN：9789866432354
裝訂：平裝

　　本書是針對嵌入式開發平台AndeShape TM ADP-XC5FF676（ADP-XC5平台）編著的實習教材，編排的方式以實例圖解的方式說明軟體開發平台建置與每一實習單元的實作過程。第一章以解說軟體開發平台安裝過程與軟體啟動為主，第二章以基本的程式範例說明軟體開發平台建置專案的過程，其餘各章節以週邊元件的控制為例說明各元件的使用控制與軟體開發過程，使用的週邊元件包含萬用串列輸出入（UART）、通用輸出入（GPIO）、軟硬體中斷、七段顯示器、看門狗、LCD文字及圖形顯示。以上各章節皆以實例操作輔以實作過程的截圖，為讀者詳細解說每一步驟的作法，相信讀者依循圖解的說明定能完成軟體平台的安裝與每一章節的實作。

作者簡介
周志學
　　中正大學電機博士
　　現任崑山科技大學資工系副教授
研究領域：嵌入式微算機、嵌入式系統、數位通訊網路、展頻分碼多工系統

設定AICE-MCU Clock time

1. 使用滑鼠點選,桌面for MCU版本的ICEman.

2. 輸入〝ICEman.exe --p 1234 –c 9〞將預設為48MHz改成24MHz.

3. 使用者可以輸入〝ICEman.exe --h〞可以查看有那些參數可以設定.

AndesCore-N903-S

Benefit
Performance
*16/32bit mixable instruction format for compacting code density
*Static branch predication
*Low-latency vectored interrupt for real-time performance
*Completion of one 32-bit operation per cycle
*Hardware divider and fast or small multiplier

Flexibility
*Memory-mapped I/O space
*PC-relative jumps for position independent code
*JTAG-based debug support
*Support for bi-endian data accesses
*Several configurations to trade off between core size and application requirements

Power Management
*Highly clock-gated pipeline
*Power management instructions
Product Information@0.13um

a. Frequencies are synthesized for 50MHz and estimated maximum for worst case
b. Estimated based on the minimal configuration of Core+ BIU+ vector interrupt controller,

General Descriptions
N903-S is a synthesizable softcore of general purpose 32-bit embedded processor. It is suitable for cost and power sensitive applications that require small footprint and manageable power consumption.
N903-S is delivered with complete development package for ease of integration in SoC design by simulation environment, as well as reference design flow to fit customer’s requirement in all aspects of performance, power consumption and core size and suitable for 8bit/16bit MCU upgrade applications.

Functional Blocks

Key Features
CPU Core
*AndeStar V2 and V2j architecture
*16 or 32 general-purpose 32-bit registers
*5-stage pipeline
*Multiply-add and Multiply-subtract instructions
*Aligned post-increment load/store single
*Aligned and unaligned load/store multiple
*Vectored interrupts with 6 signals for interrupt source and 2 runtime options
**Use the built-in internal interrupt controller for 6 interrupt sources
**Use the external interrupt controller with 64 interrupt sources
*2 or 3 HW nested interruption levels
*Memory-mapped I/O
*Non-Translated-Mapping(NTM) for cacheability attribute
*Optional 4GB or 16MB address space

Memory Subsystem
*I & D cache
**Cache size: 4KB to 32KB
**Cache line size: 16B/32B
**Set associativity: direct-mapped or 2-way
**I cache locking support
*External I & D local memory (LM)
**Size: 1KB to 1MB

Bus Interface
*APB/AHB/AHB-Lite
*AMI (Andes Memory Interface)

Debug Support
*JTAG debug interface
*Embedded debug module (EDM)

Miscellaneous
*Programmable data endian control

Development Tools
N903-S supported by two advanced development
tools
*AndeSight™ :
Integrated development environment
*AndESLive™ :
ESL integrated virtual environment

Applications *Home media centers
*Portable media players
*Digital photo frames
*E-learning devices
*Game consoles
*Electronic/music Toys

AndesCore-N1033A-S

Benefit
Performance
*Audio acceleration DSP extension
*Burst support for uncached load multiple
*Efficient atomic access synchronization without locking system bus
*Low latency vectored interrupt improving real-time performance
*Zero-wait-state local memory with 1D/2D DMA
*Low power mode
*MMU
**HW page table walker
**TLB management instructions
*MPU
**Memory protection regions

Flexibility
*Memory-mapped IO space
*PC-relative jumps for position independent code
*JTAG-based debug support
*Performance monitors for performance tuning
*Bi-endian data accesses

Power management
*Clock-gated pipeline
*Low-power mode support instructions

Applications
*PMP
*Music player
*DVD
*Game
*DSC
*Storage

General descriptions
N1033A-S is a synthesizable softcore of general purpose 32-bit embedded processor with DSP extension instructions. With those powerful instructions, N1033A-S can play compressed audio music with very low frequency and power.
Besides, N1033A-S comes with a variety of configuration options including MMU/MPU, cache and local memory. It can be applied for performance sensitive applications that running embedded Linux as well as cost and power sensitive applications that require small footprint or real-time OS and manageable power consumption.
N1033A-S is delivered with a complete development package for ease of integration in SoC design by its user-friendly configuration tool, simulation environment, as well as reference design flow to fit customer’s requirement in all aspects of performance, power consumption and core size.

Functional blocks

Key features
CPU core
*AndeStar™ V2 architecture
*16/32bit mixable instruction format
*32 general-purpose 32-bit registers
*5-stage pipeline
*Dynamic branch prediction with 32/64/128-entry BTB
*Multiply-Accumulate and Multiply-subtract instructions
*Post-increment aligned load/store single
*Aligned and unaligned load/store multiple
*Vector interrupts for internal/external interrupt controller
*3 HW-level nested interruptions
*User and super-user mode support
*Memory-mapped I/O and up to 4GB address space

Memory management unit
*TLB
**4/8-entry fully associative iTLB/dTLB
**32/64/128-entry 4-way set-associative main TLB
**TLB locking support
*Hardware page table walker
*Two groups of page size support
**4KB & 1MB
**8KB & 1MB

Memory protection unit
*8 memory protection regions

Memory subsystem
*I & D cache
**Virtually indexed and physically tagged
**Cache size: 4KB to 32KB
**Cache line size: 16B/32B
**Set associativity: 2 way
**I cache locking support
*I & D local memory (LM)
**Internal or external to CPU core and size up to 1MB
**Optional 1D/2D DMA engine

Bus interface
*Synchronous/Asynchronous AHB bus
*Port number: 1 AHB-lite, 1AHB, or 2AHB
(instruction port and data port)

Audio acceleration DSP extension
*Over 40 audio instructions
*Zero overhead loop mechanism
*Circular buffer mechanism
*Bit reversal addressing
*DSP-like X-Y data memory for parallel dual-load operations
*Single instruction multiple operations (SIMO)
*16-/24-/32- bit data integer/fixed-point data format
*Saturation
*12MHz for 128Kbps MP3 decode

Power management
*Power management instructions
*Clock-gated pipeline
*Software-programmable size/associativity reduction for caches, MTLB and BTB

Debug
*JTAG debug interface
*Embedded debug module (EDM)
*Optional embedded program tracer interface

Miscellaneous
*Programmable data endian control
*Performance monitoring mechanism

Development tools
N1033A-S supported by two advanced development tools
*AndeSight™ :
Integrated development environment
*AndESLive™ :
ESL integrated virtual environment

AndesCore-N1213-S

Benefit
Performance
*High speed memory access operations
*Efficient atomic access synchronization without locking system bus
*Low latency vectored interrupt improving real-time performance
*Zero-wait-state local memory with 1D/2D DMA
*MMU
**Optional HW page table walker
**TLB management instructions

Flexibility
*Memory-mapped IO space
*PC-relative jumps for position independent code
*JTAG-based debug support
*Performance monitors for performance tuning
*Bi-endian modes to support flexible data input

Power management
*Clock-gated pipeline
*Low-power mode support instructions

Applications
*Digital TV
*Digital Home
*Set top Box
*MFP
*Networking
*Switch/Router
*Communication
*Smart Phones

General descriptions
N1213-S is a synthesizable softcore of general purpose 32-bit embedded processor, with variety of configuration options including MMU, cache and local memory. It can be configured for performance sensitive applications that running embedded Linux or other advanced operating systems, as well as cost and power sensitive applications that require small footprint and manageable power consumption.
N1213-S is delivered with complete development package for ease of integration in SoC design by its user-friendly configuration tool, simulation environment, as well as reference design flow to fit customer’s requirement in all aspects of performance, power consumption and core size.

Functional blocks

Key Features
CPU core
*16/32bit mixable instruction format
*32 general-purpose 32-bit registers
*8-stage pipeline
*Dynamic branch prediction
*32/64/128/256 BTB
*return address stack (RAS)
*Multiply-Accumulate and Multiply-subtract instructions
*Post-increment aligned load/store single
*Aligned and unaligned load/store multiple
*Vector interrupts for internal/external interrupt controller with 6 hardware interrupt signals
*3 HW-level nested interruptions
*User and super-user mode support
*Memory-mapped I/O
*Address space up to 4GB

Memory management unit
*TLB
**4/8-entry fully associative iTLB/dTLB
**32/64/128-entry 4-way set-associative main TLB
**TLB locking support
*Optional hardware page table walker
*Two groups of page size support
**4KB & 1MB
**8KB & 1MB

Memory subsystem
*I & D cache
**Virtually indexed and physically tagged
**Cache size: 8KB/16KB/32KB/64KB
**Cache line size: 16B/32B
**Set associativity: 2/4-way
**Direct map option : 2/4 bank
**Cache locking support
*I & D local memory (LM)
**Size: 4KB to 1MB
**Bank numbers: 1 or 2
**Optional 1D/2D DMA engine
**Internal or external to CPU core

Bus Interface
*Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports
*Synchronous High speed memory port (HSMP): 0, 1 or 2 ports

Power management
*Power management instructions
*Clock-gated pipeline
*Software-programmable size/associativity reduction for caches, MTLB and BTB

Debug
*JTAG debug interface
*Embedded debug module (EDM)
*Optional embedded program tracer interface

Miscellaneous
*Programmable data endian control
*Performance monitoring mechanism

Development Tools
N1213-S supported by two advanced development tools
*AndeSight™ :
Integrated development environment
*AndESLive™ :
ESL integrated virtual environment

AndesCore-N801-S

Benefit
Performance
*16/32bit mixable instruction format for compacting code density
*Low-latency vectored interrupt for real-time performance
*Completion of most 32-bit operations in one cycle
*Fast or small multiplier
*Hardware divider

Flexibility
*Memory-mapped I/O space
*PC-relative jumps for position independent code
*JTAG-based debug support
*Fixed big or little endian support

Power Management
*Highly clock-gated pipeline
*Power management instructions

General Descriptions
N801-S is a low power small size synthesizable softcore of general purpose 32-bit embedded processor. With competitive small core size, high power efficiency and V3m ISA’s smaller code size, It is the best candidate to replace 8051 or other 8-bit MCU for cost and power sensitive applications that require small footprint and manageable power consumption.
N801-S is delivered with complete development package and small size MCU library for ease of integration in SoC design by simulation environment, as well as reference design flow to fit customer’s requirement in all aspects of performance, power consumption, cost and easy to use development tool and cost effective development board.

Functional Blocks

Key Features
CPU Core
*AndeStar V3m architecture
*3-stage pipeline
*16 general-purpose 32-bit registers with 2R1W ports
*Direct support up to 16 interrupts
*2 HW nested interruption levels
*Memory-mapped I/O
*Choice of multiplier
**Fast(1cycle) for performance
**Small(32cycle) for size
*Hardware divider for performance
*Clock gating and logic gating to reduce power
*Fully piped integration of the core and BIU for low latency
*16MB address space

Memory Subsystem
*Optional external I & D local memory(LM)
**Size: 1KB to 1MB

Bus Interface
*AHB-Lite-APB

Debug Support
*JTAG debug interface
*Embedded debug module (EDM)

Development Tools
N801-S supported by two advanced development
tools
*AndeSight™ :
Integrated development environment
*AndESLive™ :
ESL integrated virtual environment

Applications
*Medical devices
*Smart energy monitor and control
*Home security and remote control
*Gas/water/Electronic metering
*Industrial of Things (IOT)
*PC/NB peripheral
*Smart/music/education Toys
*sensor

RISC CPU效能比較的迷思

目前CISC的架構,就只有X86指令集架構,在指令集相同下,不管使用什麼樣的效能測試程式基本上是非常公平的.
但是在屬於RISC架構的CPU下,較常見的指令集架構為ARM,MIPS,Andes,Power PC,很多人會依據的衡量標準為MIPS(million instructions per second).

MIPS=指令數/執行時間x10 6

這樣就會出現下列的問題:
1. 不同架構的CPU,每個指令處裡程式的能力,是有差異的,所以只比較相同架構的CPU,會比較有意義.
2. CPU時脈不同,我相信大家都知道,就算是同一片晶圓切割下來的每一顆CPU,基本是時脈都會有差異,時脈快的,執行程式效率較好,時脈慢的,執行程式效率較差.
3. 在相同指令集架構下,但是CPU架構有做版本上的修改,CPU設計公司也會去修改架構,讓CPU效能提升,這時就算是比較相同指令集架構,所顯示出效能的結果也是會有差異.
4. 編譯器效能的差異,效能好的編譯器,可以將C編譯出比較少的指令數,當編譯出的指令數有差異時,相對的指令數少的,顯示出的效能結果當然比較好.
5. 測試程式的內容,不同的指令集架構,會有各家架構的對於某方面功能的優勢,例如:網路資料能力,浮點運算,數學運算能力...等等,如果效能測試程式只針對某部份測試,這樣測試出的結果,是很可議的.

以上是小弟我的淺見.

AndeSight v1.3.3 教學

晶心科技AndeSight v1.3.3 教學投影片,撰寫的非常詳細,照步驟操作因該就可以學會這套軟體.
AndeSight V1.3.3這套軟體,其實包含了AndeSight和AndESLive兩部分,AndeSight是撰寫開發程式的IDE介面工具,AndESLive是使用AndesCore SoC ESL模擬的平台.

下載路徑:
http://cid-b01cb9ac20175eaa.skydrive.live.com/self.aspx/About%20AndeSight%20v1.3.3%20%e6%95%99%e5%ad%b8/About%20AndeSight%20v1.3.3-20100224.zip

AndeSight v1.4 for Linux安裝

1. 開發環境:
(1). CPU: Andes RISC CPU core_N12.
(2). 平台: ADP-XC5FF676 V1.1.
(3). Linux OS: Ubuntu10.04 LTS.
(4). Toolchains: AndeSight v1.4 for Linux.
2. 安裝AndeSight v1.4 for Linux版:
(1). 將光碟送至光碟機,開啟檔案〝Disk1->Startup.sh〞.