AndesCore-N1213-S

Benefit
Performance
*High speed memory access operations
*Efficient atomic access synchronization without locking system bus
*Low latency vectored interrupt improving real-time performance
*Zero-wait-state local memory with 1D/2D DMA
*MMU
**Optional HW page table walker
**TLB management instructions

Flexibility
*Memory-mapped IO space
*PC-relative jumps for position independent code
*JTAG-based debug support
*Performance monitors for performance tuning
*Bi-endian modes to support flexible data input

Power management
*Clock-gated pipeline
*Low-power mode support instructions

Applications
*Digital TV
*Digital Home
*Set top Box
*MFP
*Networking
*Switch/Router
*Communication
*Smart Phones

General descriptions
N1213-S is a synthesizable softcore of general purpose 32-bit embedded processor, with variety of configuration options including MMU, cache and local memory. It can be configured for performance sensitive applications that running embedded Linux or other advanced operating systems, as well as cost and power sensitive applications that require small footprint and manageable power consumption.
N1213-S is delivered with complete development package for ease of integration in SoC design by its user-friendly configuration tool, simulation environment, as well as reference design flow to fit customer’s requirement in all aspects of performance, power consumption and core size.

Functional blocks


Key Features
CPU core
*16/32bit mixable instruction format
*32 general-purpose 32-bit registers
*8-stage pipeline
*Dynamic branch prediction
*32/64/128/256 BTB
*return address stack (RAS)
*Multiply-Accumulate and Multiply-subtract instructions
*Post-increment aligned load/store single
*Aligned and unaligned load/store multiple
*Vector interrupts for internal/external interrupt controller with 6 hardware interrupt signals
*3 HW-level nested interruptions
*User and super-user mode support
*Memory-mapped I/O
*Address space up to 4GB

Memory management unit
*TLB
**4/8-entry fully associative iTLB/dTLB
**32/64/128-entry 4-way set-associative main TLB
**TLB locking support
*Optional hardware page table walker
*Two groups of page size support
**4KB & 1MB
**8KB & 1MB

Memory subsystem
*I & D cache
**Virtually indexed and physically tagged
**Cache size: 8KB/16KB/32KB/64KB
**Cache line size: 16B/32B
**Set associativity: 2/4-way
**Direct map option : 2/4 bank
**Cache locking support
*I & D local memory (LM)
**Size: 4KB to 1MB
**Bank numbers: 1 or 2
**Optional 1D/2D DMA engine
**Internal or external to CPU core


Bus Interface
*Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports
*Synchronous High speed memory port (HSMP): 0, 1 or 2 ports

Power management
*Power management instructions
*Clock-gated pipeline
*Software-programmable size/associativity reduction for caches, MTLB and BTB

Debug
*JTAG debug interface
*Embedded debug module (EDM)
*Optional embedded program tracer interface

Miscellaneous
*Programmable data endian control
*Performance monitoring mechanism

Development Tools
N1213-S supported by two advanced development tools
*AndeSight™ :
Integrated development environment
*AndESLive™ :
ESL integrated virtual environment